What is the pace of China;s semiconductor chip development?

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What the chips themselves say, who is measuring them, and where China is actually gaining

By Jeffrey A. Newman, Esq. MBA with AI assistance

October 2026

In late 2025, a Huawei smartphone went on sale in China with a processor that no Chinese factory was supposed to be able to make. Within weeks, engineers in Ottawa had sawed it open and measured its wiring under an electron microscope. In June 2026, a second laboratory in Oregon did the same and published the numbers: the finest wires on the chip are 32.5 billionths of a meter apart, tighter than the equivalent wires on Intel’s newest laptop chip. The same report found that the chip performs like an Android flagship from three years ago, that its central processing core is a 2021-class design, and that it was built with a manufacturing process that appears on no official roadmap from China’s own foundry.

Those two findings sit side by side in the same report, and together they are the honest answer to the question in the title. China is advancing, measurably and fast in some places. China is not catching the leaders, measurably and by a wide margin in others. Which of those sentences you hear depends on which number someone chose to show you.

This report in brief

The short answer: China’s chipmaking is advancing on almost every front, but at very different speeds, and the fastest gains are not the fodder of headlines.

Leading-edge logic. China’s top foundry, SMIC, has delivered three generations of its 7-nanometer-class process in about four years. Its newest chips match the density of a process that Taiwan’s TSMC put into volume production around 2020, a gap of roughly five years, and the gap in speed and power efficiency is wider. Each further step is expected to be harder and slower.

Memory. This is where China is closing fastest. Korea’s chip industry association now puts China about one year behind in NAND flash, two years in DRAM and three years in the high-bandwidth memory that AI chips need. That last gap is what limits how many AI chips China can build.

AI chips and machines. The most capable Chinese AI chips examined so far were built largely from parts made in Taiwan and Korea before the controls tightened. China’s prototype EUV lithography machine makes light but not yet chips; Beijing wants working chips from it by 2028, and people close to the project say 2030. Outside lithography, Chinese toolmakers have gone from 10 to 15 percent of their home market to about 35 percent in a few years.

Volume. In older, mature-node chips, China is not behind at all. It held a third of world capacity for these chips in 2023 and is expected to build nearly half of all new capacity over the next few years.

What follows. Section I explains who measures China’s chips and how. Sections II and III take apart SMIC’s manufacturing process and the Kirin 9030 phone chip. Section IV covers memory, V Huawei’s Ascend AI chips, VI the machines that make chips, and VII mature-node volume. Section VIII asks how fast China’s engineers are learning, IX gives the answer layer by layer, and X sets out what cannot be known from outside.

How this report was built

None of what follows is speculation. Every figure is drawn from a physical teardown of a production chip, a company’s own disclosure, a report from the U.S.-China Economic and Security Review Commission, or a named research organization whose methods are stated. Where a figure is a model rather than a measurement, it is labeled as one. Where sources disagree, both are shown.

This article is about what China is building for itself, not what it is taking from anyone. It walks through the chips layer by layer, from the foundry process to memory to the machines that make them, and asks the same question of each: how far behind, and closing at what speed. It ends with a section on what cannot be known from the outside, which turns out to be the most important section of all.

I. How you measure a chip you are not allowed to see

China’s leading foundry, Semiconductor Manufacturing International Corporation, does not publish a roadmap for its most advanced processes. It does not report yields, costs, or volumes by node. Huawei does not say where its chips are made. So the question of how fast China is moving cannot be answered from Chinese disclosures. It has to be answered by people who buy the products and take them apart, and by people who build models from supply-chain data and public records.

The four kinds of watchers

There are, broadly, four kinds of watcher, and one interested reader. Each produces a different kind of knowledge.

a) TechInsights, the teardown firm

The first is the teardown firm. TechInsights, based in Ottawa, has done this work for decades. It buys production devices, removes the chips, strips them layer by layer, and measures what it finds. In 2023 it established that the Huawei Mate 60 Pro ran on a 7-nanometer-class process from SMIC[1], which its vice chair said demonstrated what China’s industry could do without the EUV lithography machines it is barred from buying. In October 2024 it found that Huawei’s Ascend 910B AI processor contained dies made by TSMC in Taiwan, which raised questions about whether Huawei had skirted sanctions. In late 2025 it confirmed that the Kirin 9030 in the Mate 80 Pro Max was made on SMIC’s third-generation 7-nanometer process, which it calls N+3, and that in absolute terms N+3 remains substantially less scaled than the 5-nanometer processes of TSMC and Samsung.

Beijing’s response tells you how much that work matters. In October 2025, China’s Ministry of Commerce added TechInsights and its affiliates in the United States, Europe, Japan and South Korea to its “unreliable entity list,” barring them from trade and investment in China.

In June 2026, TechInsights got a competitor. SemiAnalysis, a six-year-old research firm best known for its newsletter, announced that it had spent a year and a half building a teardown laboratory in Oregon and published its first public report from it, on the Kirin 9030. The report’s measurements are the backbone of the next two sections.

b) The modelers

SemiAnalysis also publishes capacity forecasts; so do Wall Street banks, consultancies, and specialist research shops. These are estimates built from equipment shipments, supplier interviews and inference. They are useful and they are not measurements.

c) The policy analysts

The third is the policy analyst. The Center for Strategic and International Studies in Washington, the U.S.-China Economic and Security Review Commission created by Congress, and the Korea Semiconductor Industry Association all publish assessments. Their numbers come from trade data, company filings, and industry interviews. Their strength is scope; their weakness is that they are synthesizing other people’s measurements.

d) The market-research houses: Mordor Intelligence

The fourth is the market-research house. Mordor Intelligence, for example, publishes forecasts of China’s chip market size and capacity share. These are useful for the shape of demand and much less useful for the question of technical capability. One Mordor claim, that SMIC’s sites offer over 1.2 million 12-inch wafer starts per month, is roughly double what industry reporting and SMIC’s own figures support, and another, that domestic producers remain confined to 28 nanometers for mass production, is contradicted by every teardown above. Market forecasts and physical evidence are different instruments.

e) Nvidia, the Overlord

One more fact belongs here. As part of its case to be allowed to sell AI chips to China, Nvidia prepared a report warning that Huawei could soon have the flexibility to satisfy global AI chip demand. According to The Wire China, which reviewed it in July 2026, the report did not rest on Nvidia’s own modeling; it cited estimates from outside groups, including CSIS, SemiAnalysis, Bernstein and Morgan Stanley. The company with the most money at stake was reading the same outside watchers everyone else reads. Keep that in mind in the final section.

II. The main engine: three generations of a 7-nanometer manufacturing process in four years

The pace of China’s chip development is, at the leading edge, the pace at which SMIC improves one family of manufacturing processes. SemiAnalysis reported that SMIC had begun shipping its first 7-nanometer process, N+1, nearly four years before June 2026. The Kirin 9000s of 2023 used N+2. The Kirin 9030 of late 2025 uses N+3. Three generations in roughly four years is a brisk pace.

It helps to be clear about what kind of pace it is. All three are refinements of the same 7-nanometer family. Over roughly the same four years, TSMC began volume production of an entirely new 3-nanometer generation in late 2022, and of a 2-nanometer generation, built with a new type of transistor, in late 2025. SMIC is improving quickly within one generation; the leaders are moving from one generation to the next.

What those generations delivered can now be stated in numbers, because two laboratories have measured them.

What the measurements mean

Picture a chip as a city of tiny switches, called transistors, joined by wires. How many switches fit on a patch of silicon depends mainly on two measurements: the height of each standard building block, called a cell, and the spacing between switches along a row.

SemiAnalysis measured both on N+3. Each cell is 228 nanometers tall, 9.5 percent shorter than the 252 nanometers on N+2. The switches sit 57 nanometers apart, also 9.5 percent closer than before. The finest wires were squeezed 19 percent closer, to 32.5 nanometers apart, and the small memory cells built into the chip shrank about 19 percent, though SemiAnalysis notes that part of that was catch-up, because N+2’s memory cells were unusually large.

Put the two cell measurements together and the same patch of silicon holds about 22 percent more transistors than one generation earlier. That figure is computed from SemiAnalysis’s measurements; SemiAnalysis does not state it. What it means for pace: roughly a fifth more capacity in one generation, achieved without the machines the leaders use. SemiAnalysis estimates that one more step, a theoretical N+4, could add about the same again, but with more difficulty, as the estimates below explain.

The result is a process with 113.4 million transistors per square millimeter. For comparison, TSMC’s N6, a mature node that uses EUV lithography, measures 107.7 million. SMIC, without EUV, has slightly exceeded it. That is the headline China’s defenders are entitled to.

Here is how it was done, and what it cost. Without EUV, SMIC prints the finest features by exposing the wafer multiple times with older deep-ultraviolet light, a technique called multi-patterning. The tightest layer on N+3 requires quadruple patterning. SemiAnalysis found that N+3 reaches N6-class density through aggressive DUV multi-patterning and design-technology co-optimization, and that it pays for that in complexity, efficiency and process control. More exposures mean more masks, more opportunities for misalignment, higher cost, and lower yield. The teardown found the finest trenches visibly narrower at the bottom than the top, a physical sign of the strain.

The significance

And here is the comparison that matters more than density. TSMC N6 is the comparison point because it is the closest match in density, but N6 is several generations old. SemiAnalysis notes that Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. In the plainest terms: SMIC has, in late 2025, matched the density of a TSMC process that entered volume production around 2020. On density alone, that is a gap of roughly five years, a computed comparison rather than a figure either laboratory states. On performance and efficiency the gap is wider, as the next section shows.

The estimates

What comes next is estimate rather than measurement, and the estimates are worth reading because they come from the people who did the measuring. SemiAnalysis projects that a theoretical N+4 could reach about 138 million transistors per square millimeter, on par with TSMC N5, but warns that the difficulty is cumulative and that N+4 will likely take longer, cost more, and carry less process margin than the N+2 to N+3 step. A theoretical N+5, with power delivered from the back of the wafer, could reach about 164 million, on par with Intel’s 18A high-performance library, but it would reach a similar density through a much more expensive route. Beyond that, SemiAnalysis writes, Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap.

A separate analysis published by SemiWiki, drawing on TechInsights’ data, reaches a similar conclusion from a different direction: that SMIC’s metal pitch was aggressively scaled using DUV multi-patterning, and that further scaling would require pushing beyond double patterning on more layers.[2]

III. The chip in the phone is three years old

Density is what the foundry can build. Performance is what the engineers can do with it. The Kirin 9030 answers the second question too, and the answer is more sobering for China than the first.

SemiAnalysis found that the Kirin 9030 Pro performs similarly to three-year-old Android flagships and trails far behind the current flagship chips from Apple, Qualcomm, MediaTek and Samsung, with an efficiency gap that is wider still. Its main processing core runs at 2.75 gigahertz and lands near Arm’s 2021-era Cortex-X2 per clock. Apple’s low-power core delivers 20 percent higher integer performance while drawing 1 watt, compared with 4.5 watts for Huawei’s prime core.

Apple v. Huawei

That is the number to hold onto. Apple’s small, efficiency core beats Huawei’s big, flagship core while using less than a quarter of the power. The reason is not that Huawei’s engineers are weak. SemiAnalysis is explicit that matching older high-end cores per clock is a genuine design achievement, and that the chip’s middle and smallest cores improved by double digits per clock over the previous generation. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes. The design is competent. The foundry underneath it is five years behind, and that is what the phone’s battery feels.

Two other findings from the same teardown say something about what China’s engineers have learned.

The first concerns software. Chip design depends on electronic design automation tools, and the dominant ones are American. Huawei has been barred from them since it was placed on the U.S. Entity List. SemiAnalysis concludes that Huawei had domestic EDA tools and flows before the Kirin 9030, having shipped multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. That is a capability built under sanction, and it is real. The same report notes that Huawei used only a single standard-cell library on the chip, where TSMC customers mix two, which it attributes to the smaller customer base and more constrained domestic design and EDA ecosystem. The tools exist; the ecosystem around them is thin.

The second concerns the path around the wall. At a conference in 2026, Huawei presented what it calls LogicFolding, a plan to stack active logic vertically so that the longest wires get shorter and performance recovers what the foundry cannot provide. Its published roadmap targets a prime-core frequency rising from 2.75 gigahertz to roughly 5 gigahertz by 2031, and a density figure of 295 million transistors per square millimeter in the same year. SemiAnalysis notes that the density claim is not directly comparable to foundry densities, because a stacked design can report more transistors per package footprint by adding active layers. Measured the same way, it adds, an AMD accelerator due in 2026 would already exceed Huawei’s 2031 target. The roadmap is ambition stated in a frame that flatters it. The ambition is still worth knowing about, because it describes where Huawei’s engineering effort is going: packaging, stacking, and system design, the places where EUV is not required.

IV. Memory: the area moving fastest

If you want the clearest case of China making headway, it is not logic. It is memory.

In September 2026, the Korea Semiconductor Industry Association, the trade body for the country that dominates the memory business, revised its assessment of China’s two memory champions. According to the Korea JoongAng Daily’s account, the gap between Korea and China has narrowed to three years in high-bandwidth memory, two years in DRAM and one year in NAND flash. The Korean reporting characterized the pace as compressing two or three years of progress into a single year.

Not every analyst is that generous. In June 2026, a Seoul-based SemiAnalysis analyst put the gaps at about two years in NAND, three in DRAM and four in HBM. The two assessments agree on the order, with NAND closest and HBM furthest behind, and differ by about a year on each.

NAND: the closest race

The NAND case is the strongest. According to the same Korean reporting, Samsung and SK hynix began producing 300-layer NAND in 2025, while YMTC was producing 270-layer; by 2027 YMTC plans 400-layer, narrowing the gap to about a year. YMTC’s new Wuhan fab is reported to be sourcing more than half of its equipment, materials and tools from Chinese suppliers, including the tools for stacking the layers. That last detail is a telling sign of pace on its own: a leading-edge memory fab built mostly with domestic tools would have been implausible five years ago.

DRAM is next. The SemiAnalysis teardown found CXMT memory inside the 16-gigabyte Mate 80 Pro Max, with density roughly equivalent to other manufacturers’ 1z process. Samsung memory found in the same phone line is on Samsung’s 1a process, one generation newer. TechInsights separately confirmed that CXMT can manufacture DDR5 at the D1z node. A bottom-up model from Citrini Research, reported by Tom’s Hardware, estimates that CXMT will finish 2026 with about 350,000 DRAM wafer starts per month, which would be just 25,000 fewer than Micron. That is a forecast, not a count, and should be read as one.

High-bandwidth memory, the stacked DRAM that feeds AI accelerators, is where China is furthest behind, and the lag matters more than any other number in this article because, as the next section explains, it is the binding constraint on China’s AI chip output. In February 2026, CXMT was reported to be planning to devote about 20 percent of its DRAM capacity to HBM3, with mass production targeted for 2026. Not everyone expects that: TrendForce judged a large shift unlikely while ordinary memory is in short supply, and CXMT’s July 2026 stock-market prospectus earmarked none of its named spending for HBM. Counterpoint Research expects CXMT to begin producing HBM from the end of 2026. One report describes CXMT’s pilot HBM3E production at yields around 25 percent, with persistent trouble on the vertical connections between stacked dies. The Korean reporting also notes that CXMT is using a YMTC bonding technique that joins copper directly to copper between the layers, which would let it build competitive HBM without EUV. That is engineering ingenuity under constraint, the same pattern as SMIC’s multi-patterning.

V. The AI accelerator: a Chinese chip with foreign parts

Huawei’s Ascend processors are China’s answer to Nvidia, and they are the single product on which the most policy attention rests. They are also the place where the public record is most contested.

Start with what the teardowns show. TechInsights found that the Ascend 910B contained dies made by TSMC, and that the newer Ascend 950PR used the same processor, interposer and memory dies as the 910B, sourced from TSMC and Samsung or SK hynix. As of its 2026 analysis, TechInsights said it had yet to witness a China-produced Ascend chipset. SemiAnalysis estimated that TSMC provided 2.9 million dies, enough for 800,000 Ascend 910Bs and 1.05 million 910Cs across 2024 and 2025.

The most capable Chinese chips

So the most capable Chinese AI chips examined to date were substantially made outside China, from a stockpile. The question of China’s pace, for AI accelerators, is the question of whether SMIC can replace that stockpile.

Here the sources are models, and the most-cited ones are older than they look. SemiAnalysis’s conservative estimate, published in September 2025, put SMIC’s capacity at 7 nanometers and below at 45,000 wafers per month by the end of 2025, rising to 60,000 in 2026 and 80,000 in 2027, and forecast that SMIC would no longer be the bottleneck for Ascend production. A CSIS analysis published in March 2025 described SMIC as struggling with roughly 20 percent yield on Ascend chips and 20,000 7-nanometer wafers a month, and reported that SMIC was targeting 50,000 by the end of 2025. Read by date, the two capacity figures are broadly consistent; neither comes from SMIC, and both are now a year or more old. On yield, CSIS’s sources put it at about 20 percent, SemiAnalysis describes it only as poor, and nobody outside SMIC knows.

Volume: more than 805,000 Ascends in 2025 — what they could build

What the sources agree on is the bottleneck. SemiAnalysis wrote in September 2025 that China could make more than 805,000 Ascends that year from TSMC and SMIC capacity but would not, because it did not have enough HBM. A Nikkei-sourced report says CXMT plans dedicated HBM3 lines in Shanghai for domestic accelerators. Until those lines yield at volume, China’s AI chip output is set by memory, not by logic.

The ecosystem around Huawei is broadening regardless. CSIS reports that Alibaba has delivered over 100,000 units of its Zhenwu 810E AI chip, claimed comparable to Nvidia’s H20, and that at least nine Chinese AI chipmakers have exceeded 10,000 shipments or orders, including Huawei, Baidu and Cambricon. TrendForce projects that in 2026 the domestic share of China’s AI chip market will reach 50 percent, though that projection reflects Beijing’s procurement pressure as much as capability.

VI. The machines

Everything above depends on equipment, and the equipment is where the gap is widest and the Chinese effort is most intense.

Lithography

Lithography is the chokepoint. In December 2025, Reuters reported that Chinese scientists had completed a prototype extreme-ultraviolet lithography machine in a high-security Shenzhen laboratory, built partly from components of older ASML systems and by former ASML engineers. The prototype reportedly generates EUV light but has not produced a working chip; Beijing’s target for functional chips from it is 2028, and people close to the project regard 2030 as more realistic. The program is said to involve more than 3,000 researchers, with Huawei coordinating and the state-backed firm SMEE handling integration.

How far behind is that? One forecasting group, AI Futures, estimates that the prototype is roughly equivalent to ASML’s demonstration tools of 2006 or 2008, which would imply a 12-to-14-year gap to TSMC’s first commercial 5-nanometer EUV production in 2020. Another observer put the point more bluntly: ASML took 18 years from prototype to production, and Beijing wants three, with people close to the project expecting five. Both are opinions about a machine none of them has seen. Other public estimates exist, from ASML’s chief executive and from forecasters and analysts, but none rests on direct inspection either.

Domestic deep-ultraviolet tools, the generation below EUV, are further along but only now entering production. SMEE’s 28-nanometer immersion tool, announced in 2023, has reportedly never been deployed, and a public claim of its successful development was deleted shortly after publication. In December 2025, China’s Ministry of Science and Technology awarded SMEE a contract for a lithography system that some sources described as 28-nanometer-capable; on verification, the machine turned out to be a KrF tool with 110-nanometer resolution, several generations older. In July 2026, a new state-owned company that absorbed the SMEE and Huawei-linked lithography teams was reported to have begun low-volume production of immersion DUV machines: about five this year and roughly 20 planned for 2027, with the first units going to Chinese fabs for testing rather than volume output. Neither company has confirmed the report, and no machine has been shown publicly.

Everywhere except lithography, the picture is different. CSIS reports that Chinese-made equipment accounted for only 10 to 15 percent of the domestic market before the controls; that share surged from 25 to 35 percent between 2024 and 2025, exceeding the Made in China 2025 target of 30 percent, with local firms now supplying 40 percent of the domestic market in etching and thin-film deposition. One Chinese supplier, Naura, reportedly accounts for 60 percent of the oxidation and diffusion furnaces serving SMIC’s 28-nanometer production. The USCC reported a much lower figure for more advanced tools: China-based manufacturers met only 9.6 percent of domestic demand for 20-to-14-nanometer chipmaking equipment in 2023. The two figures measure different things, and together they make the same point: the gains are concentrated in older equipment.

CSIS adds the caveat that these gains probably reflect sales of equipment serving the mature nodes, and that comprehensive data on the pace of China’s localization effort is not available. That caveat applies to every number in this section.

VII. Volume: the mature-node wave

There is one part of the semiconductor business where China’s pace of development is not in dispute, because it is measured in factories rather than nanometers.

The U.S.-China Economic and Security Review Commission’s November 2025 evaluation of Made in China 2025 found that China-based firms made up 33 percent of global wafer production capacity for foundational-node logic chips in 2023, up from 19 percent in 2015, and that China’s mature-node capacity grew more than four times faster than global demand over that period. It projects that China-based chipmakers will account for nearly half of new mature-node capacity over the next three to five years. The commission’s stated concern is that China could come to dominate these segments, on which nearly every product depends. In December 2024 the U.S. Trade Representative opened an investigation into China’s mature-node practices, citing evidence of significant capacity expansion and artificially low domestic and global prices.

A note on a number you may see elsewhere. CSIS’s March 2026 commentary, citing the USCC, says Chinese capacity now accounts for about half of global capacity. The USCC’s own figure is 33 percent of capacity in 2023 and nearly half of new capacity going forward. The second is the one supported by the primary source.

Mordor Intelligence, a market-research firm, projects that China will hold 31 percent of global 28-nanometer capacity by 2027, and reports that China expanded foundry capacity 15 percent in 2024 with another 14 percent scheduled for 2025. A Shanghai-based industry report puts SMIC’s 2025 output above 10 million wafers, its utilization above 93 percent, and its capital spending at 60 to 70 percent of revenue across 2022 to 2025, a ratio typical of a company in an expansion phase. Those last figures should be checked against SMIC’s annual report before anyone relies on them.

Against all of that, one figure keeps the mature-node story in proportion. Made in China 2025 set a target of 70 percent semiconductor self-sufficiency by the end of 2025. CSIS reports that domestically produced chips accounted for about 30 percent of domestic consumption in 2025. China built the factories. It has not yet replaced the chips.

VIII. How fast China’s engineers are learning

The pace of a country’s chip development is, in the end, the pace at which its engineers learn. That is the hardest thing to measure from outside, and the public record offers fragments rather than a count.

The fragments point one way. An affiliate of the China Semiconductor Industry Association counts Chinese chip design companies growing from 736 in 2015 to 3,901 by 2025. The Shenzhen EUV program reportedly employs about 100 recent university graduates who spend their days disassembling lithography components. Researchers at Peking University have announced a prototype EDA tool for Huawei’s LogicFolding architecture. In January 2026, Zhejiang Province set targets to design and manufacture homegrown chips and equipment at the 7-to-3-nanometer nodes within five years. Shanghai and Shenzhen had already set theirs.

Mordor Intelligence reports a talent gap: China required 199,300 semiconductor professionals in 2022 and had 164,300, with shortages acute in EDA algorithm design, device physics and process-integration leadership. The sourcing for those figures is not shown, so treat them as indicative.

The teardowns say something the counts cannot. The engineers who designed the Kirin 9030 matched 2021-class performance per clock on a process five years behind the leaders, using tools they built themselves because the standard ones were taken away. The engineers at CXMT borrowed a bonding technique from a NAND maker to build HBM without EUV. The engineers at SMIC reached quadruple patterning on a layer that the leaders print with a single EUV exposure. None of that is catching up. All of it is learning, and learning compounds.

IX. So what is the pace?

Here is the answer, layer by layer, with the basis for each line.

Leading-edge logic manufacturing: three process generations in about four years, reaching the density of a TSMC node from around 2020. Gap on density about five years; gap on performance and power efficiency wider. Basis: TechInsights and SemiAnalysis teardowns. Direction: advancing, but each further step is expected to be harder and slower than the last.

Chip design and tools: shipping complete flagship processors on domestic EDA tools while cut off from Western software. Basis: SemiAnalysis teardown analysis. Direction: a capability that was not visible before the controls now is.

NAND memory: about one year behind, with a new fab built mostly on domestic equipment. Basis: Korean industry association assessment, EE Times reporting. Direction: closing.

DRAM: about two years behind by the Korean assessment; one process generation behind by the teardown. Direction: closing, with capacity growing fast.

High-bandwidth memory: about three years behind; pilot yields reported low; the binding constraint on China’s AI chip volume. Direction: closing slowly from a long way back.

AI accelerators: the most capable examined chips were built from a foreign-made stockpile; domestic production is modeled, not yet seen in a teardown. Direction: unknown until a China-made Ascend is examined.

Lithography: an EUV prototype that makes light but not chips; domestic immersion DUV only reportedly entering low-volume production. Public estimates of the EUV gap run to a decade or more, and none is based on inspection. Direction: a program with enormous resources and no measured output yet.

Other equipment: domestic share up from roughly 10 to 15 percent to 35 percent in a few years; 40 percent in etch and deposition. Direction: closing fast at mature nodes.

Mature-node volume: from 19 to 33 percent of global capacity in eight years, with nearly half of new global capacity planned in China. Direction: not a gap at all; an overhang.

Where China is making headway, the pattern is consistent. It gains fastest where the problem is manufacturing scale, process ingenuity under constraint, or substituting a tool one generation behind the best. It gains slowest where the problem is a single irreplaceable machine or the compounding advantage of a process node. Memory, mature logic, deposition and etch tools, packaging, and design software are moving. EUV, leading-edge performance, and HBM are not, or not yet.

X. What we do not know

This section is shorter than it should be, because the things in it cannot be lengthened from the outside.

Nobody outside SMIC knows its yields on N+2 or N+3, its cost per wafer, or how many wafers of each it runs. The most-cited public estimates of its capacity are a year or more old and rest on unnamed sources.

Nobody has publicly examined an Ascend accelerator made entirely in China. Every teardown to date has found foreign dies. The models say domestic production is ramping; the microscopes have not confirmed it.

Nobody outside the Shenzhen laboratory has seen the EUV prototype. Every public estimate of its maturity is an inference from what ASML’s machines looked like at a similar stage.

And the people doing the measuring have interests. TechInsights sells reports and is, according to its new competitor, owned by private equity and up for sale. SemiAnalysis sells research and custom teardowns to clients it does not name. The Korean industry association speaks for companies whose share prices move on these assessments. CSIS and the USCC are funded by donors and by Congress respectively and say so. None of that makes any of them wrong. It means that the public picture of China’s pace of progress is assembled almost entirely by private parties with reasons to publish, read by governments and companies that have, on the evidence of Nvidia’s own submission, no better picture of their own.

That is the state of knowledge in October 2026. The chips are measured to the nanometer. The factories are counted. The pace is knowable in most layers, and it is faster than the controls were designed for and slower than the headlines suggest. What is not knowable is the part that happens inside buildings no outsider enters, and it is that part, not the measured part, that will decide whether the next phone cut open in Ottawa has a Chinese chip inside it that nobody expected.

Jeff Newman Law is a national whistleblower law firm handling False Claims Act, SEC, and export control matters. The firm can be reached at www.JeffNewmanLaw.com or at 617-823-3217.

Sources

Teardowns and process analysis

AI accelerators and capacity models

Memory

Equipment and lithography

Policy and market assessments